1. Field of the Invention
The present invention relates to an information processing system and, more particularly, to an information processing system which is made operative to execute an instruction under the control of timing signals.
2. Description of the Prior Art
A computer is an example which is reprentative of such an information processing system. As is well known in the art, the computer is constructed so that it reads an instruction out of a memory and executes the processing operation in accordance with the instruction which is read out. In the execution of the instruction which is, a decoder first decodes the instruction read out and, responsive thereto, generates a variety of control signals. The control signals thus generated are required for an instruction executing unit (e.g., a central processing unit, "CPU") to execute the instruction and are prepared in accordance with the instruction which are read out. Those control signals include many signals such as signals for fetching the information to a register, signals for controlling the conduction and non-conduction of a gate, signals for writing and reading the information into and out of an input/output port, signals for reading the information out of a memory or register, or signals for controlling the execution of logic arithmetic such as addition or subtraction.
These control signals are usually generated simultaneously, from a decoder. If the generated control signals are simultaneously fed to respective circuits, however, a disturbance never fails to occur in the information, thereby to invite a malfunction of the computer. Therefore, the sequence has to be controlled so that the control signals are fed to the respective circuits in accordance with the execution sequence of the instruction. For this reason, timing signals are used. These timing signals are generated at a predetermined time interval by dividing the frequency of the clock pulses having the maximum frequency, and the divided signals are usually called the "status signals".
The executions of the respective instructions are designed so that the sequence of control is effected by a plurality of status signals, and the set of that plurality of status signals are called the "machine cycle". In other words, it can be said that the instructions are executed with reference to the machine cycle. Therefore, the respective instructions are defined as 1 machine cycle instruction, 2 machine cycles instruction and so on in accordance with the length of the time period which is required for their executions. If the 1 machine cycle is composed of four status signals, eight status signals are required to execute the 2 machine cycles instruction.
The aforementioned control signals have their timings controlled by those status signals and are fed to the respective circuits. As a result, the CPU can correctly execute the respective instructions on the basis of the control signals (i.e., the decoder outputs), which have their timings controlled. Incidentally, the status signals can also be used as the timing control signals for not only the CPU, but also in either the memory or the input/output port. Moreover, the timing control of the computer is fixed by those status signals.
However, the timing control by the status signals have disadvantages as will be described in the following specification. Specifically, since the computer has its timing control fixed by the status signals, the timing control in the cooperation with another device is remarkably complex. It is very difficult to control all the devices, which are to be coupled to the computer, with the same timing that is used to control the computer. This is because the operating speeds of the respective devices are generally different. Thus, to control all the devices with an identical timing requires an adjustment of all operating speeds to conform to the device having the slowest operating speed. However, this remarkably reduces the processing speed to make it impossible to satisfy the requirement for the high speed processing operation.
Moreover, a computer such as a microcomputer, which is constructed on a small semiconductor chip by the use of a circuit integrating technique, cannot be equipped with many external terminals for information transmission. Therefore, the computer of that kind has to be coupled by the use of a limited number of terminals to another device such as another microcomputer, a memory or a peripheral device such as a key board or a display device. In this case, the timing control of either the microcomputer or a system (e.g., a multi-processor system) including a microcomputer is a remarkably difficult and important problem.
Moreover, the development of the microcomputer is escalating. Especially, the single chip microcomputer in all of the functions of a computer, such as the memory function, the instruction executing function or the input/output function of data are incorporated into a single silicon substrate. The enlargement of the kinds of the instructions to be executed by such a microcomputer, as well as the memory capacity and the input/output function are abruptly advanced in accordance with the progress of a super LSI technique.
Therefore, as the microcomputer has its function thus improved and its hardware circuit made more complicated, its testing mechanism naturally raises a problem. Especially, the single chip microcomputer cannot unlimitedly increase the number of the input and output terminals to be used for the data transmission with the external devices. In addition, most of those terminals have to be assigned as ports for information transmission. As a result, it is remarkably difficult to provide for the tests such as the confirmation of the instruction execution or the function confirmation of the internal memory.
According to the prior art, there is a first method, in which the test instruction for the operation confirmation of an executing unit and memories is preset in a predetermined area of a read only memory being used as a program memory (which will be referred to as a "program ROM"). The test instruction is a program (i.e., an instruction group) for performing the test of the executing unit and the memories.
A second method uses the same terminal for the information transmission with the outside (i.e., the input/output port) and for the testing terminal so that the aforementioned test instruction can be given from the outside.
According to the first method, however, a partial area of the program ROM is occupied for setting the testing instruction. Thus, there arises a disadvantage in that the number of instructions to be set in the memory for the program processing operation is reduced. It can be predicted without fail that the numbers of the program processing instructions and the testing instructions will be increased, especially in accordance with the enlargement of the processing function. In this case, the reduction in the instruction numbers appears as a remarkably large disadvantage.
According to the second method, on the other hand, since the input/output port for the information transmission is used as an input port for the test instruction, its intrinsic function is lost. In short, it has been impossible to confirm the input and output operations of that port.
Especially, it has been impossible to execute the input and output instructions to test whether or not information can be correctly fed from the input/output port and whether or not the information can be fed to the input/output port. In order to execute those tests, the control signals based upon the input/output instructions and their timing signals (i.e., the status signals) have to be fed under a predetermined condition to the input/output port. However, since the input/output port is used as an input for the test instruction, it has become impossible to receive the control signals having their timings controlled by the status signals.